1. Field of Invention
The present invention relates to the field of enhancement mode gallium nitride (GaN) heterojunction field effect transistors (HFET). In particular, the invention relates to methods for more cost-effective fabrication of enhancement mode GaN devices and integrated circuits.
2. Description of the Related Art
Gallium nitride (GaN) semiconductor devices are increasingly desirable for power semiconductor devices because of their ability to carry large current and support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heterojunction/heterostructure field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET).
A GaN HFET device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer cause the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
The nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because the 2DEG region exists under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted (i.e., removed) below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide and because they are easier to control with simple, low cost drive circuits. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
In GaN devices and integrated circuits, isolation is typically used to remove the 2DEG at a selected area. Isolation reduces parasitic capacitances, for example, gate-to-drain capacitance and drain-to-source capacitance. FIG. 1 illustrates an exemplary integrated circuit with two device 10 and 20 in which isolation area 12 in device 10 and isolation area 22 in device 20 are provided to intentionally remove the 2DEG to minimize parasitic capacitance. Isolation placed at certain areas of the devices can also reduce electric field.
In a GaN integrated circuit, isolation is used to enable different reference potentials for each device. For example, in FIG. 1, isolation area 24 electrically separates device 10 and device 20 so that the source of device 10 and the source of device 20 will be at different potentials. Isolation areas 12 and 22 inside the devices 10 and 20 remove the 2DEG where it is undesirable, thereby reducing parasitic capacitances and in some cases removing areas with higher electric field.
FIG. 2 illustrates another exemplary integrated circuit having device 30 and device 40 with isolation. Device 30 includes drain 31, gate 32 and source 33. Likewise, device 40 includes drain 41, gate 42 and source 43. An isolation area 50 electrically separates device 30 and device 40, so that the source 33 of device 30 and the source 43 of device 40 will be at different potentials. Device 30 includes isolation area 34 and device 40 includes isolation area 44 to remove the 2DEG where it is undesirable, thereby reducing parasitic capacitances and in some cases removing areas with higher electric field.
In conventional manufacturing methods, to fabricate isolation area 50 between adjacent devices 30 and 40 and to fabricate isolation areas 34 and 44 inside the devices 30 and 40, conductive layers and the 2DEG are removed by etching or ion-implantation. FIGS. 3A and 3B illustrate a cross-section of line AA′ from FIG. 2, where the isolation area 50a, 50b is formed by said etching and said ion-implantation, respectively.
As shown FIGS. 3A and 3B, the isolation areas 50a and 50b have a length LISO that determines the maximum voltage differential between the source 33 of the first device 30 and the source 43 of the second device 40. In GaN based materials, the breakdown voltage may be proportional to LISO with 50˜200V per μm.
Conventionally, the isolation area 50 is fabricated with a dedicated mask. As shown in FIGS. 4A and 4B, in fabricating the isolation area 50 with etching or ion-implantation 60, a dedicated isolation mask is used to form a patterned photoresist 62 on top of the wafer. The isolation areas 50c and 50d are exposed while the device regions of device 30 and device 40 are covered with the patterned photoresist 62.
Conventional manufacturing methods to form the isolation area 50 includes several process steps, including, for example, photolithography, etch or ion-implantation, photoresist strip, and wafer cleaning. Ion-implantation isolation may additionally require a thermal anneal to active the implanted ion species. A dedicated isolation mask and its associated process steps increase fabrication cost.
Accordingly, there is a strong felt need for a manufacturing method of GaN semiconductor devices that forms an isolation area, with a self-aligned isolation region, that avoids the above-mentioned disadvantages and additional process steps.